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| 3D3314 MONOLITHIC QUAD FIXED DELAY LINE (SERIES 3D3314) FEATURES * * * * * * * * * * * All-silicon, low-power 3.3V CMOS technology Vapor phase, IR and wave solderable Auto-insertable (DIP pkg.) Low ground bounce noise Leading- and trailing-edge accuracy Delay range: 10ns through 400ns Delay tolerance: 2% or 0.5ns (3.3V, 25C) Temperature stability: 1% typical (0C-70C) Vdd stability: 1% typical (3.0V-3.6V) Static Idd: 1.3ma typical Minimum input pulse width: 25% of total delay I1 NC I2 I3 I4 NC GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 PACKAGES VDD NC O1 NC O2 O3 O4 I1 NC I2 I3 I4 NC GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD NC O1 NC O2 O3 O4 3D3314-xx DIP-14 3D3314D-xx SOIC-14 For mechanical dimensions, click here. For package marking details, click here. FUNCTIONAL DESCRIPTION The 3D3314 device is a small, versatile, quad fixed monolithic delay line. Delay values ranging from 10ns through 400ns may be specified via the device dash number. Each input is reproduced at the corresponding output without inversion, shifted in time as per user selection. The 3D3314 is 3.3V CMOS-compatible and features both rising- and fallingedge accuracy. The device is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount 14-pin SOIC. PIN DESCRIPTIONS I1-I4 O1-O4 VDD GND NC Signal Inputs Signal Outputs 3.3V Ground No Connection TABLE 1: PART NUMBER SPECIFICATIONS PART NUMBER 3D3314-10 3D3314-15 3D3314-20 3D3314-25 3D3314-30 3D3314-40 3D3314-50 3D3314-75 3D3314-100 3D3314-125 3D3314-150 3D3314-200 3D3314-250 3D3314-300 3D3314-400 DELAY AND TOLERANCE (ns) 10.0 1.0 15.0 1.0 20.0 1.0 25.0 1.0 30.0 1.0 40.0 1.0 50.0 1.0 75.0 1.5 100 2.0 125 2.5 150 3.0 200 4.0 250 5.0 300 6.0 400 8.0 INPUT RESTRICTIONS RECOMMENDED Max Freq Min P.W. 40.0 MHz 12.5 ns 26.6 MHz 18.8 ns 20.0 MHz 25.0 ns 16.0 MHz 31.3 ns 13.3 MHz 37.5 ns 10.0 MHz 50.0 ns 8.00 MHz 62.5 ns 5.33 MHz 93.8 ns 4.00 MHz 125.0 ns 3.20 MHz 156.3 ns 2.66 MHz 187.5 ns 2.00 MHz 250.0 ns 1.60 MHz 312.5 ns 1.33 MHz 375.0 ns 1.00 MHz 500.0 ns ABSOLUTE Max Freq Min P.W. 166 MHz 3.0 ns 166 MHz 3.0 ns 166 MHz 3.0 ns 166 MHz 3.0 ns 166 MHz 3.0 ns 125 MHz 4.0 ns 100 MHz 5.0 ns 66.6 MHz 7.5 ns 50.0 MHz 10.0 ns 40.0 MHz 12.5 ns 33.3 MHz 15.0 ns 25.0 MHz 20.0 ns 20.0 MHz 25.0 ns 16.6 MHz 30.0 ns 12.5 MHz 40.0 ns NOTES: Any dash number between 10 and 400 not shown is also available as standard 2002 Data Delay Devices Doc #00120 6/12/02 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 1 3D3314 APPLICATION NOTES OPERATIONAL DESCRIPTION The 3D3314 quad fixed delay line architecture is shown in Figure 1. Each delay line is composed of a number of delay cells connected in series. Each delay line produces at its output a replica of the signal present at its input, shifted in time. The delay lines are matched and share the same compensation signals, which minimizes line-toline delay deviations over temperature and supply voltage variations. Table 1 delay accuracy for input frequencies higher than the Recommended Maximum Frequency, the 3D3314 must be tested at the user operating frequency. Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. The programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted. INPUT SIGNAL CHARACTERISTICS The Frequency and/or Pulse Width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Recommended Maximum and an Absolute Maximum operating input frequency and a Recommended Minimum and an Absolute Minimum operating pulse width have been specified. OPERATING PULSE WIDTH The Absolute Minimum Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest Pulse Width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. The Recommended Minimum Pulse Width (high or low) specification determines the smallest Pulse Width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed. To guarantee the Table 1 delay accuracy for input pulse width smaller than the Recommended Minimum Pulse Width, the 3D3314 must be tested at the user operating pulse width. Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the O2 O3 O4 OPERATING FREQUENCY The Absolute Maximum Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. The Recommended Maximum Frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed. To guarantee the VDD O1 Temp & VDD Compensation Delay Line Delay Line Delay Line Delay Line GND I1 I2 I3 I4 Figure 1: 3D3314 Functional Diagram Doc #00120 6/12/02 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 2 3D3314 intended frequency and duty cycle of operation. Doc #00120 6/12/02 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 3 3D3314 APPLICATION NOTES (CONT'D) The programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. Small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted. minimize the delay variations induced by fluctuations in power supply and/or temperature. The thermal coefficient is reduced to 200 PPM/C, which is equivalent to a variation, over the 0C70C operating range, of 1% or 0.25ns (whichever is greater) from the 25C delay settings. The power supply coefficient is reduced, over the 3.0V-3.6V operating range, to 1% or 1ns (whichever is greater) of the delay settings at the nominal 3.3VDC power supply. It is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should be of as low an impedance construction as possible. Power planes are preferred. . POWER SUPPLY AND TEMPERATURE CONSIDERATIONS The delay of CMOS integrated circuits is strongly dependent on power supply and temperature. The monolithic 3D3314 delay line utilizes novel and innovative compensation circuitry to DEVICE SPECIFICATIONS TABLE 2: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature SYMBOL VDD VIN IIN TSTRG TLEAD MIN -0.3 -0.3 -1.0 -55 MAX 7.0 VDD+0.3 1.0 150 300 UNITS V V mA C C NOTES 25C 10 sec TABLE 3: DC ELECTRICAL CHARACTERISTICS (0C to 70C, 3.0V to 3.6V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current Low Level Output Current Output Rise & Fall Time SYMBOL IDD VIH VIL IIH IIL IOH IOL TR & TF MIN 2.0 -0.1 -0.1 0.0 0.0 -8.0 7.5 2 0.8 0.1 0.1 -6.0 TYP 1.3 MAX 2.0 UNITS mA V V A A mA mA ns NOTES VDD = 3.6V VIH = VDD VIL = 0V VDD = 3.0V VOH = 2.4V VDD = 3.0V VOL = 0.4V CLD = 5 pf 6.0 *IDD(Dynamic) = 4 * CLD * VDD * F where: CLD = Average capacitance load/line (pf) F = Input frequency (GHz) Input Capacitance = 10 pf typical Output Load Capacitance (CLD) = 25 pf max Doc #00120 6/12/02 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 4 3D3314 SILICON DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: Ambient Temperature: 25oC 3oC Supply Voltage (Vcc): 3.3V 0.1V Input Pulse: High = 3.3V 0.1V Low = 0.0V 0.1V Source Impedance: 50 Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) Pulse Width: PWIN = 1.5 x Total Delay Period: PERIN = 3.0 x Total Delay OUTPUT: Rload: Cload: Threshold: 10K 10% 5pf 10% 1.5V (Rising & Falling) Device Under Test 10K 5pf Digital Scope 470 NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. COMPUTER SYSTEM PRINTER REF PULSE GENERATOR OUT TRIG IN1 DEVICE UNDER IN2 TEST (DUT) IN3 IN4 OUT1 OUT2 OUT3 OUT4 IN TRIG DIGITAL SCOPE/ TIME INTERVAL COUNTER Figure 2: Test Setup PERIN PW IN tRISE INPUT SIGNAL 2.4 1.5 0.6 tFALL VIH 2.4 1.5 0.6 VIL tPHL tPLH OUTPUT SIGNAL 1.5 VOH 1.5 VOL Figure 3: Timing Diagram Doc #00120 6/12/02 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 5 |
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